1. Field of the Invention
The present invention relates to zero detection, and more particularly to detecting whether a difference of binary operands is zero.
2. Description of Related Art
In general purpose computers, program control is often implemented using conditional branches. In general, conditional branches are used in any programming situation in which one of two possible paths for continuing computation must be chosen. The branch decision is usually based on an arithmetic or logic property, or condition, of the result of a recently performed operation. The branch decision may be based, for instance, on whether a single operand is zero, positive or negative. The branch decision may also be based on whether a first operand is greater than, greater than or equal to, equal to, less than or equal to, or less than a second operand. These conditions are usually evaluated by inspecting condition code bits, or flags, in a condition code register. Computer systems often have four condition code flags: N (negative), C (carry), V (overflow), and Z (zero). The negative flag is set to one if the result is negative and is otherwise set to zero. The carry flag is set to one if a carry-out results from the operation and is otherwise set to zero. The overflow flag is set to one if an arithmetic overflow occurs and is otherwise set to zero. Finally, the zero detect flag is set to one if the result is zero and is otherwise set to zero.
A zero detect flag (or zero flag) based on a difference of the operands indicates whether the operands are equal. When the operands are equal, the difference between the operands is zero, and the zero detect flag is set to TRUE. Likewise, when the operands are unequal, the difference between the operands is nonzero, and the zero detect flag is set to FALSE. In this manner, zero detect of a binary difference can provide the Z (zero) condition code flag for a branch decision.
The difference of two binary operands (A-B) is obtained by subtracting the subtrahend (B) from the minuend (A). In 2's complement representation, the sign of the subtrahend is changed by adding one to the bit-complement of the subtrahend. The binary difference can be provided using a forced carry technique, in which the minuend and the bit-complemented subtrahend are applied to an adder, and the carry-in bit for the least significant bit position of the adder is set to one. In this manner, the difference of A-B is obtained by applying A and the bit-complement of B to a sum-plus-one adder.
Zero detection determines whether every bit in a string of bits is a zero. That is, if a string of bits contains all zero's then the zero detect flag is set to TRUE, whereas if the string of bits contains a one (or several one's) then the zero detect flag is set to FALSE.
FIG. 1 illustrates a known circuit 100 for performing zero detection of a difference of two n-bit binary operands A and B. The B operand is applied to inverter circuit 102 that provides a bit-complemented B operand (B) at its output. The operands A and B are applied to a sum-plus-one adder, shown as a carry lookahead adder which includes PG generator 104, carry chain 106 having a carry-in bit set to one, and sum generator 108. Although other adders can be used, the carry lookahead adder provides a sum more rapidly than, for instance, a carry-ripple adder. The n-bit sum of operands A and B and one, which represents the difference of A-B, is provided by output stages n-1, n-2, . . . 1, 0 of sum generator 108. Zero detect logic is provided by n-input OR gate 110 and inverter 112. OR gate 110 has inputs coupled to each output stage of sum generator 108. OR gate 110 outputs a logical 0 when the bit string in the output stages consists of zero's, and outputs a logical 1 when the bit string in the output stages includes any one's. Inverter 112 complements the output of OR gate 110. Thus, the output of inverter 112 provides a zero detect flag for the difference of operands A and B. Drawbacks to this approach include the increased fan-in of OR gate 110, and delays associated with calculating the difference of A and B and ORing each bit of the difference.
Another known technique for zero detect of a binary difference includes calculating the difference, serially right-shifting the difference, and inspecting the shifted-out bits one at a time. As soon as a shifted-out bit is detected as being a one, the zero detect flag is set to FALSE. Alternatively, if all shifted-out bits are zero's then the zero detect flag is set to TRUE. A drawback to this approach is that the right-shifting operation can be relatively time consuming, and particularly difficult to implement in a single instruction cycle.
Accordingly, there is a need for performing zero detect of a difference of binary numbers in a rapid and efficient manner.